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CY7C1345G
4-Mbit (128K x 36) Flow Through Sync SRAM
Features

Functional Description
The CY7C1345G is a 128K x 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. The maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1345G enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses are initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) is active. Subsequent burst addresses are internally generated as controlled by the Advance pin (ADV). The CY7C1345G operates from a +3.3V core power supply while all outputs operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
128K x 36 common IO 3.3V core power supply (VDD) 2.5V or 3.3V IO supply (VDDQ) Fast clock-to-output times 6.5 ns (133 MHz version) Provide high performance 2-1-1-1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed write Asynchronous output enable Available in Pb-free 100-Pin TQFP package, Pb-free and non-Pb-free 119-Ball BGA package ZZ Sleep Mode option

Selection Guide
Parameter Maximum Access Time Maximum Operating Current Maximum Standby Current 133 MHz 6.5 225 40 100 MHz 8.0 205 40 Unit ns mA mA
Cypress Semiconductor Corporation Document Number: 38-05517 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 15, 2007
CY7C1345G
Logic Block Diagram
A 0, A1, A
ADDRESS REGISTER A [1:0]
MODE
ADV CLK
BURST Q1 COUNTER AND LOGIC Q0 CLR
ADSC ADSP DQ D, DQP D BW D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B, DQP B BYTE WRITE REGISTER DQ A , DQP A BW A BWE GW CE1 CE2 CE3 OE DQ A , DQPA BYTE WRITE REGISTER BYTE WRITE REGISTER DQ D, DQP D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B, DQP B BW B BYTE WRITE REGISTER
BW C
MEMORY ARRAY
SENSE AMPS
OUTPUT BUFFERS
DQ s DQP A DQP B DQP C DQP D
ENABLE REGISTER
INPUT REGISTERS
ZZ
SLEEP CONTROL
Document Number: 38-05517 Rev. *E
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CY7C1345G
Pin Configurations
100-Pin TQFP Pinout
BWD BWC BWB BWA CE3 CE1 VDD VSS OE ADSC ADSP ADV 86 85 84 83 CE2 CLK GW A BWE A 82 A A 81
99
98
97
96
95
94
93
92
91
90
89
88
DQPC DQC DQC VDDQ VSSQ DQC DQC BYTE C DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD
BYTE D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
100
87
CY7C1345G
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA BYTE B
BYTE A
38
39
40
41 VDD
42 NC/18M
NC/72M NC/36M
MODE A
NC/9M A A
A1
A0
VSS
A
A
A
43
A
A
A A
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A
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CY7C1345G
Pin Configurations (continued)
119-Ball BGA Pinout 1 A B C D E F G H J K L M N P R T U VDDQ NC/288M NC/144M DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A CE2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC/72M NC 3 A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A NC 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A NC 5 A A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A NC 6 A CE3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC/36M NC 7 VDDQ NC/576M NC/1G DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ
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CY7C1345G
Pin Definitions
Name A0, A1, A IO Description Input Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two-bit counter. Input Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Synchronous Sampled on the rising edge of CLK. Input Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). Input Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted Synchronous LOW to conduct a byte write. Input Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
BWA, BWB BWC, BWD GW BWE CLK CE1
Input Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Input Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. Input Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. Input Output Enable, asynchronous Input, Active LOW. Controls the direction of the IO pins. When Asynchronous LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Input Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increSynchronous ments the address in a burst cycle. Input Address Strobe from Processor, sampled on the rising edge of CLK, Active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Input Address Strobe from Controller, sampled on the rising edge of CLK, Active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Input ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep Asynchronous condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin has an internal pull down. IO Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and DQP[A:D] are placed in a tri-state condition. Power Supply Power supply inputs to the core of the device. Ground IO Power Supply IO Ground Ground for the core of the device. Power supply for the IO circuitry. Ground for the IO circuitry.
CE2
CE3
OE
ADV ADSP
ADSC
ZZ
DQs DQPA, DQPB DQPC, DQPD
VDD VSS VDDQ VSSQ
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CY7C1345G
Pin Definitions (continued)
Name MODE IO Input Static Description Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode Pin has an internal pull up. No Connects. Not Internally connected to the die. - No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M, and NC/1G are address expansion pins and are not internally connected to the die.
NC NC/9M, NC/18M, NC/36M NC/72M, NC/144M, NC/288M, NC/576M, NC/1G
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO) is 6.5 ns (133 MHz device). The CY7C1345G supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable and is determined by sampling the MODE input. Accesses are initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wrap around burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, and CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
Single write access is initiated when the following conditions are satisfied at clock rise: 1. CE1, CE2, and CE3 are all asserted active 2. ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWx) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. Byte writes are allowed. During byte writes, BWA controls DQA and BWB controls DQB, BWC controls DQC, and BWD controls DQD. All IOs are tri-stated during a byte write. Since this is a common IO device, the asynchronous OE input signal is deasserted and the IOs are tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are satisfied at clock rise: 1. CE1, CE2, and CE3 are all asserted active. 2. ADSC is asserted LOW. 3. ADSP is deasserted HIGH 4. The write input signals (GW, BWE, and BWx) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter or control logic and delivered to the memory core. The information presented to DQ[D:A] is written into the specified address location. Byte writes are allowed. During byte writes, BWA controls DQA, BWB controls DQB, BWC controls DQC, and BWD controls DQD. All IOs and even a byte write are tri-stated when a write is detected. Since this is a common IO device, the asynchronous OE input signal is deasserted and the IOs are tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE.
Single Read Accesses
A single read access is initiated when the following conditions are satisfied at clock rise: 1. CE1, CE2, and CE3 are all asserted active. 2. ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs are deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter or control logic and presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH.
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CY7C1345G
Burst Sequences
The CY7C1345G provides an on-chip two-bit wrap around burst counter inside the SRAM. The burst counter is fed by A[1:0] and follows either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Table 1. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
Table 2. Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. In this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device is deselected prior to entering the sleep mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min Max 40 2tCYC Unit mA ns ns ns ns
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CY7C1345G
Truth Table
The truth table for CY7C1345G follows. [1, 2, 3, 4, 5] Cycle Description Deselected Cycle, Power down Deselected Cycle, Power down Deselected Cycle, Power down Deselected Cycle, Power down Deselected Cycle, Power down Sleep Mode, Power down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L X X L L L L L X X H H X H X X H H X H CE2 X L X L X X H H H H H X X X X X X X X X X X X CE3 X X H X X X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV WRITE X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L OE X X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Q Tri-State D Q Tri-State Q Tri-State Q Tri-State D D Q Tri-State Q Tri-State D D
Notes 1. X = "Do Not Care," H = Logic HIGH, and L = Logic LOW. 2. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a "Do Not Care" for the remainder of the write cycle. 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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CY7C1345G
Truth Table for Read or Write
The partial truth table for read or write follows. [1, 6] Function Read Read Write Byte (A, DQPA) Write Byte (B, DQPB) Write Bytes (B, A, DQPA, DQPB) Write Byte (C, DQPC) Write Bytes (C, A, DQPC, DQPA) Write Bytes (C, B, DQPC, DQPB) Write Bytes (C, B, A, DQPC, DQPB, DQPA) Write Byte (D, DQPD) Write Bytes (D, A, DQPD, DQPA) Write Bytes (D, B, DQPD, DQPA) Write Bytes (D, B, A, DQPD, DQPB, DQPA) Write Bytes (D, B, DQPD, DQPB) Write Bytes (D, B, A, DQPD, DQPC, DQPA) Write Bytes (D, C, A, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X
Note 6. This table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is done based on the active byte write.
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CY7C1345G
Maximum Ratings
Exceeding the maximum ratings may shorten the battery life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VDD Relative to GND ........-0.5V to +4.6V Supply Voltage on VDDQ Relative to GND.......-0.5V to +VDD DC Voltage Applied to Outputs in tri-state............................................. -0.5V to VDDQ + 0.5V
DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, Method 3015) .................................. >2001V Latch up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD VDDQ 3.3V 2.5V -5% -5%/+10% to VDD
Electrical Characteristics
Over the Operating Range [7, 8] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[7] for 3.3V IO, IOH = -4.0 mA for 2.5V IO, IOH = -1.0 mA for 3.3V, IO, IOL= 8.0 mA for 2.5V IO, IOL = 1.0 mA for 3.3V IO for 2.5V IO for 3.3V IO for 2.5V IO Input Leakage Current except GND VI VDDQ ZZ and MODE Input Current of MODE Input Current of ZZ IOZ IDD ISB1 ISB2 ISB3 ISB4 Output Leakage Current Input = VSS Input = VDD Input = VSS Input = VDD GND VI VDDQ, Output Disabled 7.5 ns cycle, 133 MHz 10 ns cycle, 100 MHz -5 VDD Operating Supply Current VDD = Max, IOUT = 0 mA, f = fMAX= 1/tCYC Automatic CE Power down Current--TTL Inputs Automatic CE Power down Current--CMOS Inputs Automatic CE Power down Current--CMOS Inputs Automatic CE Power down Current--TTL Inputs -5 30 5 225 205 90 80 40 2.0 1.7 -0.3 -0.3 -5 -30 5 Test Conditions Min 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max 3.6 VDD Unit V V V V V V V V V V A A A A A A mA mA mA mA mA
Max VDD, Device Deselected, 7.5 ns cycle, 133 MHz VIN VIH or VIN VIL, f = fMAX, 10 ns cycle, 100 MHz inputs switching Max VDD, Device Deselected, All speeds VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static Max VDD, Device Deselected, 7.5 ns cycle, 133 MHz VIN VDDQ - 0.3V or VIN 10 ns cycle, 100 MHz 0.3V, f = fMAX, inputs switching Max VDD, Device Deselected, All speeds VIN VDD - 0.3V or VIN 0.3V, f = 0, inputs static
75 65 45
mA mA mA
Notes 7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 8. TPower up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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CY7C1345G
Capacitance
Tested initially and after any design or process change that may affect these parameters. Parameter CIN CCLK CIO Description Input Capacitance Clock Input Capacitance Input or Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V 100 TQFP Max 5 5 5 119 BGA Max 5 5 7 Unit pF pF pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100 TQFP Package 30.32 6.85 119 BGA Package 34.1 14.0 Unit C/W C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50
R = 317 VDDQ 5 pF GND R = 351 10%
ALL INPUT PULSES 90% 90% 10% 1ns
VT = 1.5V
1ns
(a) 2.5V I/O Test Load
OUTPUT Z0 = 50
INCLUDING JIG AND SCOPE 2.5V
(b)
R = 1667 VDDQ GND R = 1538 10%
(c)
ALL INPUT PULSES 90% 90% 10% 1 ns
OUTPUT RL = 50 VT = 1.25V
(a)
5 pF INCLUDING JIG AND SCOPE
1 ns
(b)
(c)
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CY7C1345G
Switching Characteristics
Over the Operating Range [9, 10] Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise GW, BWE, BWx Hold After CLK Rise ADV Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Setup Before CLK Rise ADSP, ADSC Setup Before CLK Rise ADV Setup Before CLK Rise GW, BWE, BWx Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low Clock to High Z[12, 13, 14] Z[12, 13, 14] 2.0 0 3.5 3.5 0 3.5 0 3.5 Z[12, 13, 14] 6.5 2.0 0 3.5 3.5 8.0 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 2.5 2.5 10 4.0 4.0 ns ns ns Description VDD(Typical) to the first Access[11] -133 Min 1 Max -100 Min 1 Max Unit ms
OE LOW to Output Valid OE LOW to Output Low Z[12, 13, 14] OE HIGH to Output High
Notes 9. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 10. Test conditions shown in (a) of Latch up Current >200 mA unless otherwise noted. 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation is initiated. 12. tCHLZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured 200 mV from steady state voltage. 13. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions. 14. This parameter is sampled and not 100% tested.
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CY7C1345G
Timing Diagrams
Figure 1 shows the read cycle timing. [15] Figure 1. Read Cycle Timing
tCYC
CLK
t
CH
t CL
t ADS
tADH
ADSP
t ADS tADH
ADSC
t AS tAH
ADDRESS
A1
t WES t WEH
A2
GW, BWE,BW
[A:B] t CES t CEH
Deselect Cycle
CE
t ADVS t ADVH
ADV ADV suspends burst OE
t OEV t CLZ t OEHZ t OELZ
t CDV t DOH t CHZ
Data Out (Q)
High-Z
Q(A1)
t CDV
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around to its initial state
Single READ DON'T CARE
BURST READ UNDEFINED
Note: 15. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
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CY7C1345G
Timing Diagrams
(continued)
Figure 2 shows the write cycle timing. [15, 16] Figure 2. Write Cycle Timing
t CYC
CLK
t
CH
t
CL
t ADS
tADH
ADSP
t ADS tADH
ADSC extends burst
t ADS tADH
ADSC
t AS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP initiates burst
A3
t WES tWEH
BWE, BW [A:B]
t WES t WEH
GW
t CES tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t DS t DH D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2)
Data in (D)
High-Z
t
D(A1) OEHZ
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Note: 16. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW.
Document Number: 38-05517 Rev. *E
Page 14 of 20
CY7C1345G
Timing Diagrams
(continued)
Figure 3 shows the read and write timing. [16, 17, 18] Figure 3. Read/Write Timing
tCYC
CLK
t
CH
t
CL
t ADS
tADH
ADSP
ADSC
t AS tAH
ADDRESS
A1
A2
A3
t WES t WEH
A4
A5
A6
BWE, BW
[A:B] t CES tCEH
CE
ADV
OE
t DS tDH t OELZ
Data In (D) Data Out (Q)
High-Z
t OEHZ
D(A3)
t CDV
D(A5)
D(A6)
Q(A1)
Q(A2) Single WRITE DON'T CARE
Q(A4)
Q(A4+1) BURST READ UNDEFINED
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
Back-to-Back READs
Notes: 17. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 18. GW is HIGH.
Document Number: 38-05517 Rev. *E
Page 15 of 20
CY7C1345G
Timing Diagrams
(continued)
Figure 4 shows the ZZ mode timing. [19, 20] Figure 4. ZZ Mode Timing
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
A LL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 19. Device must be deselected when entering ZZ mode. See "Truth Table" on page 8 for all possible signal conditions to deselect the device. 20. DQs are in high-Z when exiting ZZ sleep mode.
Document Number: 38-05517 Rev. *E
Page 16 of 20
CY7C1345G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1345G-133AXC CY7C1345G-133BGC CY7C1345G-133BGXC CY7C1345G-133AXI CY7C1345G-133BGI CY7C1345G-133BGXI 100 CY7C1345G-100AXC CY7C1345G-100BGC CY7C1345G-100BGXC CY7C1345G-100AXI CY7C1345G-100BGI CY7C1345G-100BGXI Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
lndustrial
Commercial
lndustrial
Document Number: 38-05517 Rev. *E
Page 17 of 20
CY7C1345G
Package Diagrams
Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document Number: 38-05517 Rev. *E
0.10
R 0.08 MIN. 0.20 MAX.
Page 18 of 20
CY7C1345G
Package Diagrams (continued)
Figure 6.119-Ball BGA (14 x 22 x 2.4 mm), 51-85115
O0.05 M C O0.25 M C A B A1 CORNER O0.750.15(119X) O1.00(3X) REF. 1 A B C E F G 22.000.20 H J K L M N P R T U 10.16 19.50 20.32 1.27 D 2 34 5 6 7 7 6 5 4321 A B C D E F G H J K L M N P R T U
1.27 0.70 REF. A 3.81
12.00 B 2.40 MAX.
7.62 14.000.20
0.900.05
0.25 C
30 TYP.
0.15(4X) 0.15 C
SEATING PLANE
0.56
C 600.10
51-85115-*B
Document Number: 38-05517 Rev. *E
Page 19 of 20
CY7C1345G
Document History Page
Document Title: CY7C1345G, 4-Mbit (128K x 36) Flow Through Sync SRAM Document Number: 38-05517 REV. ** *A ECN NO. Issue Date 224365 278513
See ECN See ECN
Orig. of Change RKF VBL New datasheet
Description of Change Deleted 66 MHz Changed TQFP package to Pb-free TQFP in Ordering Information section Added BG Pb-free package Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA Packages as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced `Snooze' with `Sleep' Removed 117 MHz speed bin Replaced TBDs for JA and JC to their respective values on the Thermal Resistance table Removed comment on the availability of BG Pb-free package Updated the Ordering Information by shading and unshading MPNs as per availability Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Modified test condition from VIH < VDD to VIH < VDD. Modified test condition from VDDQ < VDD to VDDQ < VDD Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B Updated the Ordering Information Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Updated the Ordering Information table. Corrected Write Cycle timing waveform
*B
333626
See ECN
SYT
*C
418633
See ECN
RXU
*D *E
480124 1274724
See ECN See ECN
VKN VKN
(c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05517 Rev. *E
Revised July 15, 2007
Page 20 of 20
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.

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